Current mode converters are a well known type of switching power supply which provide efficient operation over a wide range of operating conditions. These converters may be designed in either a voltage step-up (boost) or voltage step-down (buck) configuration.
In a typical voltage mode boost converter, an inductor is placed between a power supply and the drain of a switching transistor. A diode is coupled between the common inductor/drain terminal and the output of the converter. As the switching transistor is turned on and off under the control of a pulse width modulator, the inductor is energized with a current which flows through the inductor and switching transistor to ground, thus storing energy in the core of the inductor in the form of a magnetic flux. When the switching transistor is turned off, current continues to flow through the inductor. As the magnetic flux field collapses, a voltage appears across the inductor which is delivered through a diode to the load. Typically, a large capacitor is placed across the output of the converter to hold the converter output voltage at a predetermined level during the periods when the switching transistor is charging the inductor. In a voltage controlled converter, the voltage appearing at the load is sensed by an error amplifier through a voltage divider network. The error amplifier generates an error voltage which is related to the voltage appearing at the output of the converter. Minute changes in voltage appearing at the output of the converter are changed to relatively larger voltage swings by the error amplifier. The output of the error amplifier is coupled to one terminal of a comparator which has another terminal coupled to a fixed frequency ramp signal. As the voltage appearing at the output of the error amplifier rises and falls with respect to the ramp signal voltage, the output of the comparator changes state in a pulse-width modulated waveform. This signal is coupled to the switching transistor to effect the switching thereof and complete the regulator loop.
In a current mode converter, a peak current detection scheme is employed in the generation of the pulse width modulated control signal. Specifically, a sensing resistor is placed in series with the switching transistor and inductor. The series resistor senses the current flow in the inductor. The switching transistor is typically controlled by a flip/flop which is set to provide a high output by a clock signal having a predetermined frequency. Whenever the output of the flip-flop is high, the switching transistor turns on. When the switching transistor is turned on, current flow will begin to build in the inductor and the switching transistor. The voltage appearing across the current sensing resistor is coupled to a comparator which detects a predetermined voltage level. As the voltage appearing across the sensing resistor rises above the predetermined voltage level, the output of the comparator changes state and resets the flip/flop, thereby turning off the switching transistor until the next clock cycle. Thus, in a current mode converter, the inductor charging cycle is initiated by a fixed frequency clock signal and is terminated once the peak inductor current reaches a predetermined level. The rate at which the current flow changes during an inductor charging cycle is referred to as the slope of the current waveform.
Current mode converters offer several advantages over voltage mode converters. Current mode converters offer a simple topology. Since the inductor is switched on and off based on peak inductor current flow, the need for a separate pulse width modulator circuit is eliminated. Furthermore, the transient response of the current mode converter is much improved.
While the current mode converter offers many advantages, it has certain disadvantages. These disadvantages are discussed in B. Holland, Modeling, Analysis and Compensation Of The Current Mode Converter, Powercon II Proceedings, paper I-2, 1984. Holland and others have demonstrated that current mode converters exhibit the problems of open-loop instability above 50% duty cycle, less than ideal loop response caused by peak rather than loop sensing, and a tendency toward subharmonic oscillation and noise sensitivity, particularly when inductor current is small.
Holland has demonstrated that many of these problems may be significantly reduced by adding slope compensation to the sensed current waveform. Holland has demonstrated that the slope of the compensation ramp must be greater than one-half of the down slope of the current waveform. Thus, for a buck regulator, where the down slope is a constant equal to R.sub.s (VO/L) the amplitude (A) of the slope compensation should be chosen such that EQU A&gt;T.multidot..sup.R.sbsb.s .spsb.(V.sub.O.spsb./L)
to guarantee stability above a 50% duty cycle where:
V.sub.O =voltage at the output of the converter PA1 T=converter switch period PA1 R.sub.s =current sense resistor resistance PA1 L=inductance in mH of the inductor
While this technique renders the converter stable under all load conditions, the linearity and transient response of the converter will be severely degraded at light loads.
One technique for improving the performance of a current mode converter is discussed in U.S. Pat. No. 4,672,518, invented by Murdock, and incorporated herein by reference. This patent discloses a technique wherein a fixed slope ramp signal is summed with the sensed current waveform for slope compensation at light loads. Under heavy loads, the compensation signal is disabled or switched to a second reduced fixed slope. While this technique recognizes that a compensating ramp signal optimized for one mode of operation may not be suitable for another mode of operation, only two levels of fixed slope compensation are provided.
While Holland and Murdock have demonstrated that slope compensation will improve the performance of a current mode converter, all known slope compensation techniques employ fixed slope compensation. That is, the sensed current waveform is summed with a ramp signal having a fixed slope and the resultant signal is coupled to the comparator which controls the flip/flop and switching transistor. No technique is known which provides only the required amount of slope compensation for present operating conditions.
Furthermore, known slope compensation techniques are based on circuits which are operated from highly filtered DC power sources. Fixed slope compensation is not useful in circuits which are powered by a source of unfiltered power, for example the unfiltered output of a rectifier bridge. In this case, the power supply varies sinusoidally between zero volts and the power supply voltage. As the input voltage varies, the amount of required slope compensation also varies. In a fixed slope compensation system, a variable input voltage results in distortion in the sinusoidal envelope of the average current in the inductor. Further, circuits requiring a smooth DC input voltage generally employ a large electrolytic filter capacitor which causes poor line input power factor and are known to be unreliable. The present invention eliminates the need for this capacitor, thus improving the input line power factor and reliability over prior converters.
Finally, prior teachings have not addressed the problem of the effect of slope compensation on power factor. Fixed slope compensation causes poor power factor at light loads and high line voltages. In situations where the power factor of the converter is critical, known current mode converters are not suitable since the power factor of these circuits will change as the input voltage to the circuit changes. No prior technique is known which allows a current mode converter to incorporate a controlled variable slope compensation in a circuit which operates from an unfiltered or partially filtered power source while maintaining a nearly perfect power factor.